Extended Chip-Package co-simulation

Market development of microchips is characterized by a contradiction: the components are becoming smaller and more complex, yet also cheaper.

This implies that the conventional design process– whereby a prototype is tested and optimized - is no longer possible. "First Time Right" is today’s principle - and a chip that does not fulfill the function for which it was designed at the first attempt can lead to immense damage for its manufacturer. CISC Semiconductor Design + Consulting GmbH has developed a simulation software to test the functioning of such System-in-Package (SIP) designs to ensure their performance level before they go into production. Extended Chip-Package Co-Simulation (ECOS) is a software tool for the automated creation of models for the simulation of parasitic effects in a SIP chip design. For this combination of technology and IT consulting, the jury of the 2008 Austrian State prize for Consulting awarded CISC the “interdisciplinary award”.

CISC Semiconductor - Klagenfurt, Austria